Phase change memory

ABSTRACT

A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of Taiwan Patent Application No.097151765, filed on Dec. 31, 2008, the entirety of which is incorporatedby reference herein.

BACKGROUND

1. Technical Field

The present disclosure relates to phase change memories (PCMs).

2. Description of the Related Art

Phase change materials have at least two phases: a crystalline phase,and an amorphous phase. A phase change memory uses phase changematerials as storage elements therein (hereinafter named phase changestorage elements). A crystalline phase is represented as logic ‘0’ andan amorphous phase is represented as logic ‘1’.

The transformation between the crystalline phase and the amorphous phaseis controlled by an operating current flowing through the phase changestorage element. Table 1 is a comparison of operating current for acrystalline phase and an amorphous phase.

TABLE 1 Comparison of write current for a crystalline phase and anamorphous phase. Operating current (in pulse form, oscillating betweenhigh and low voltage levels) magnitude duty period crystalline phase LowLong amorphous phase High ShortAchieving complete crystallization is difficult. For example, aninappropriate operating current may result in incompletecrystallization, which affects reliability of the phase change storageelement.

BRIEF SUMMARY

The disclosure unveils phase change memories. The phase change memorycomprises a phase change storage element, a transistor for operatingcurrent adjustment and a control circuit. The transistor for operatingcurrent adjustment has a first terminal coupled to a voltage source, asecond terminal coupled to the phase change storage element, and acontrol terminal receiving a control signal from the control circuit.The control circuit uses the control signal to limit the transistor in alinear region.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure can be more fully understood by reading thesubsequent detailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1A depicts an exemplary embodiment of the phase change memory ofthe disclosure;

FIG. 1B depicts another exemplary embodiment of the phase change memoryof the disclosure;

FIG. 2A depicts another exemplary embodiment of the phase change memoryof the disclosure;

FIG. 2B shows waveforms depicting exemplary embodiments of the switchingsignal WE, the control signal V_(c) and the operating current I_(w) ofFIG. 2A;

FIG. 3A depicts another exemplary embodiment of the phase change memoryof the disclosure;

FIG. 3B shows waveforms of exemplary embodiments of the switching signalWE, the control signal V_(c) and the operating current I_(w) of FIG. 3A;

FIG. 4 depicts another exemplary embodiment of the phase change memoryof the disclosure; and

FIG. 5 depicts another exemplary embodiment of the phase change memoryof the disclosure.

DETAILED DESCRIPTION

The following description shows several exemplary embodiments carryingout the disclosure. This description is made for the purpose ofillustrating the general principles of the disclosure and should not betaken in a limiting sense. The scope of the disclosure is bestdetermined by reference to the appended claims.

FIG. 1A depicts an exemplary embodiment of the phase change memory ofthe disclosure. A phase change memory 100 comprises a phase changestorage element 102 which uses more than one phase, such as acrystalline state and an amorphous state, to store different logicvalues. As shown, a switch 104 is controlled by a word line 106 of thephase change memory 100. When the switch 104 is turned on, an operatingcurrent I_(w) is allowed to flow into the phase change storage element102 to read or write the phase change storage element 102. The operatingcurrent I_(w) is dependent on the statuses of a current generator 108and a operating current adjustment transistor 110. The structure of thecurrent generator 108 does not limit the scope of the disclosure and maybe replaced by other current generating circuits known by those skilledin the art. In FIG. 1A, the current generator 108 generates a currentaccording to a reference current I_(ref), and the current generator 108is coupled between a voltage source V_(DD) and the transistor 110. Inthis embodiment, the transistor 110 for operating current adjustment isrealized by a P-type metal-oxide-semiconductor (PMOS) transistor, whichhas a source, a drain and a gate working as a first terminal, a secondterminal and a control terminal of the transistor 110, respectively. Inthe following, a description of the connection of the transistor 110(PMOS) is provided. As shown in FIG. 1A, the first terminal (source) iscoupled to the voltage source V_(DD) by the current generator 108, thesecond terminal (drain) is coupled to the phase change storage element102, and the control terminal (gate) is controlled by a control signalV_(c) provided by a control circuit 112. The control circuit 112 isdesigned to limit the transistor 110 in a linear region but not in asaturated region. Note that if the voltage level of the control signalV_(c) is decreasing, then a result would be that the current value ofthe operating current I_(w) would be concurrently increasing, and if thevoltage level of the control signal V_(c) is increasing, then a resultwould be that the current value of the operating current I_(w) would beconcurrently decreasing.

When transforming the phase change storage element 102 to a crystallinephase, a gradually increased operation current I_(w) facilitates thecrystallization process. Thus, the magnitude of the operation currentI_(w) is effectively reduced. Furthermore, a gradually decreasedoperation current I_(w) facilitates the temper of the crystallization.Thus, the phase change storage element 102 can be completelycrystallized.

FIG. 1B depicts another exemplary embodiment of the phase change memoryof the disclosure, wherein the current generator 108 is realized byanother circuit. Compared to the circuit shown in FIG. 1A, the currentgenerator 108 of FIG. 1B further comprises a transistor 120. The currentgenerators 108 shown in FIGS. 1A and 1B do not limit the scope of thedisclosure, and may be replaced by other circuits known by those skilledin the art.

FIG. 2A depicts another exemplary embodiment of the phase change memoryof the disclosure, which details an exemplary embodiment of the controlcircuit 112. As shown, the control circuit 112 comprises a capacitor Cand a charge/discharge circuit 202. The capacitor C is coupled to thecontrol terminal of the transistor 110. The voltage held by thecapacitor C is the control signal V_(c). The charge/discharge circuit202 charges or discharges the capacitor C to vary the control signalV_(c) between a first pre-determined voltage V_(N) and the sourcevoltage V_(DD). The lower limit, V_(N), of the control signal V_(c)limits the transistor of the current adjuster 110 to work in a linearregion. Thus, in the example shown in FIG. 2A, when the control signalV_(c) is gradually decreased, the operating current I_(w) is graduallyincreased; and when the control signal V_(c) is gradually increased, theoperating current I_(w) is gradually decreased. The first pre-determinedvoltage V_(N) is higher than the voltage level of the ground (GND).

This paragraph details the circuit of the charge/discharge circuit 202of FIG. 2A. As shown in FIG. 2A, the charge/discharge circuit 202comprises a first current mirror 204, a second current mirror 206 and acharge/discharge switch 208. The first current minor 204 comprises apower terminal coupled to the voltage source V_(DD), a reference currentterminal for a charge reference current I_(rc) to pass through, and aload terminal outputting a charge current I_(c). The second currentminor 206 comprises a power terminal biased at the first per-determinedvoltage V_(N), a reference current terminal receiving a dischargereference current I_(rd), and a load terminal providing a dischargecurrent I_(d). The charge/discharge circuit 202 requires a bias voltageV_(in), for setting the values of the charge reference current I_(rc)and the discharge reference current I_(nt) In another embodiment, thebias voltage V_(in) may be dependent on the source voltage of thetransistor M_(in). For example, the gate and source of the transistorM_(in), may be electrically connected. and thus, the values of thecharge current I_(c) and the discharge current I_(d) are determined. Thecharge/discharge switch 208 is controlled by a switching signal WE tocouple the capacitor C to the first current mirror 204 for a chargeprocess or to the second current mirror 206 for a discharge process.

FIG. 2B shows waveforms depicting exemplary embodiments of the switchingsignal WE, the control signal V_(c) and the operating current I_(w) ofFIG. 2A. At time index t₁, the switching signal WE is switched to high,and the charge/discharge switch 208 couples the capacitor C to thesecond current mirror 206 to discharge the capacitor C. When thecapacitor C is discharged by the discharge current I_(d), the controlsignal V_(c) is decreased. At time index t₂, the switching signal WE isswitched to low, and the charge/discharge switch 208 is switched tocouple the capacitor C to the first current mirror 204 to charge thecapacitor C. When the capacitor C is charged by the charge currentI_(c), the voltage level of the control signal V_(c) is raised. Becausethe power terminals of the first and second current minors 204 and 206are biased at the source voltage V_(DD) and the first pre-determinedvoltage V_(N), respectively, the control signal V_(c) is limited betweenthe voltage levels V_(N) and V_(DD), and thus, the transistor of thecurrent adjuster 110 is operated in a linear region. According to theelectronic characteristic of a PMOS transistor that is in a linearregion, if the voltage level of the control signal V_(c) is decreasing,then a result would be that the current value of the operating currentI_(w) would be concurrently increasing, and if the voltage level of thecontrol signal V_(c) is increasing, then a result would be that thecurrent value of the operating current I_(w) would be concurrentlydecreasing. Thus, the operating current I_(w) is increased gradually andthen decreased gradually as shown in FIG. 2B.

FIG. 3A depicts another exemplary embodiment of the phase change memoryof the disclosure. Compared with the charge/discharge circuit 202 ofFIG. 2A, the charge/discharge circuit 302 of FIG. 3A further comprises afirst digital-to-analog converter 304 and a second digital-to-analogconverter 306. The first and second digital-to-analog converters 304 and306 are biased by a bias circuit 308 that is controlled by a biasvoltage V_(in). The first digital-to-analog converter 304 converts afirst digital data (D₁, D₂, D₃, D₄) to the charge reference currentI_(re) which determines the value of the charge current I_(c). Thus, therising speed of the control signal V_(c) may be determined. The seconddigital-to-analog converter 306 converts a second digital data (D₁′,D₂′, D₃′, D₄′) to the discharge reference current I_(rd) whichdetermines the value of the discharge current I_(d). Thus, thedecreasing speed of the control signal V_(c) may be determined.

FIG. 3B shows waveforms of exemplary embodiments of the switching signalWE, the control signal V_(c) and the operating current I_(w) of FIG. 3A.At time index t₁, the control signal V_(c) may be decreased at variousspeeds by different settings of the second digital data (D₁′, D₂′, D₃′,D₄′). Thus, the operating current I_(w) may be raised by various speeds.At time index t₂, the control signal V_(c) may be increased at variousspeeds by different settings of the first digital data (D₁, D₂, D₃, D₄).Thus, the operating current I_(w) may be decreased by various speeds.

In other exemplary embodiments, the control circuit 112 may comprise thefirst digital-to-analog converter 304 but not the seconddigital-to-analog converter 306. In such a case, the operating currentI_(w) has a fixed rising speed but a controllable falling speed. In someexemplary embodiments, the control circuit 112 may comprise the seconddigital-to-analog converter 306 but not the first digital-to-analogconverter 304. In such an embodiment, the operating current I_(w) has acontrollable rising speed but a fixed falling speed.

The controllable rising/falling speeds of the operating current I_(W)may be used in accomplish multi-leveled storage capability, whereinmulti-bits are stored by a single phase change storage element.

The transistor 110 is not limited to be a PMOS transistor, and may bereplaced by an N-type metal-oxide-semiconductor (NMOS) transistor. FIG.4 depicts another exemplary embodiment of the phase change memory of thedisclosure, wherein the transistor 110 is realized by an NMOStransistor. As shown in FIG. 4, a first current minor 204 has a powerterminal biased at a second pre-determined voltage V_(P) (lower thansource voltage V_(DD)) and the second current minor 206 has a groundedpower terminal. Thus, the NMOS transistor (the transistor 110) is in alinear region.

FIG. 5 depicts another exemplary embodiment of the phase change memoryof the disclosure, wherein the transistor 110 is realized by an NMOStransistor. As shown in FIG. 5, a first current mirror 204 has a powerterminal biased at a second pre-determined voltage value V_(P) that islower than the voltage VDD, and a second current minor 206 has agrounded power terminal. Thus, the NMOS transistor (the transistor 110)is in a linear region.

In some exemplary embodiments of the phase change memory of thedisclosure, the capacitor C is optional. In embodiments in which thecontrol circuit 112 does not include the capacitor C, thecharge/discharge circuit (such as circuit 202 or 302) is designed tocharge/discharge the parasitic capacitors at the control terminal of thetransistor 110. The voltage level of the control terminal of thetransistor 110 is carefully controlled, and the transistor 110 islimited in a linear region.

When the transistor 110 is realized by a PMOS transistor, thecharge/discharge circuit (such as 202 or 302 of FIGS. 2A and 3A) isdesigned to charge/discharge the parasitic capacitors at the gate of thePMOS transistor.

When the transistor 110 is realized by an NMOS transistor, thecharge/discharge circuit (such as 202 or 302 of FIGS. 4, 5) is designedto charge/discharge the parasitic capacitors at the gate of the NMOStransistor.

While the disclosure has been described by way of example and in termsof the exemplary embodiments, it is to be understood that the disclosureis not limited to the unveiled embodiments. To the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

1. A phase change memory, comprising: a phase change storage element; atransistor for operating current adjusting, having a first terminalcoupled to a voltage source, a second terminal coupled to the phasechange storage element, and a control terminal receiving a controlsignal; and a control circuit, having an output terminal coupled to thecontrol terminal of the transistor and generating the control signal tolimit the transistor in a linear region.
 2. The phase change memory asclaimed in claim 1, wherein the transistor is a P-typemetal-oxide-semiconductor (PMOS) transistor, and the first terminal,second terminal and control terminal of the transistor are a source, adrain and a gate of the PMOS transistor, respectively.
 3. The phasechange memory as claimed in claim 2, wherein the control circuitcomprises: a capacitor, coupled to the control terminal of thetransistor; and a charge/discharge circuit, charging or discharging thecapacitor to vary the control signal between a first pre-determinedvoltage and a source voltage provided by the voltage source, wherein thefirst pre-determined voltage is higher than ground.
 4. The phase changememory as claimed in claim 3, wherein the charge/discharge circuitcomprises: a first current minor, having a power terminal coupled to thevoltage source, a reference current terminal for a charge referencecurrent to pass through, and load terminal outputting a charge current;a second current minor, having a power terminal biased at the firstpre-determined voltage, a reference current terminal receiving adischarge reference current, and a load terminal outputting a dischargecurrent; and a charge/discharge switch, coupling the capacitor to theload terminal of the first current minor or the load terminal of thesecond current minor.
 5. The phase change memory as claimed in claim 4,wherein the charge/discharge circuit further comprises: a bias circuit;and a first digital-to-analog converter, biased by the bias circuit andreceiving first digital data to generate the charge reference current.6. The phase change memory as claimed in claim 4, wherein thecharge/discharge circuit further comprises: a bias circuit; and a seconddigital-to-analog converter, biased by the bias circuit and receivingsecond digital data to generate the discharge reference current.
 7. Thephase change memory as claimed in claim 2, wherein the control circuitcomprises: a charge/discharge circuit, charging or discharging parasiticcapacitors at the gate of the PMOS transistor to vary the control signalbetween a first pre-determined voltage and a source voltage provided bythe voltage source, wherein the first pre-determined voltage is higherthan ground.
 8. The phase change memory as claimed in claim 7, whereinthe charge/discharge circuit comprises: a first current minor, having apower terminal coupled to the voltage source, a reference currentterminal for a charge reference current to pass through, and a loadterminal outputting a charge current; a second current minor, having apower terminal biased at the first pre-determined voltage, a referencecurrent terminal receiving a discharge reference current, and a loadterminal outputting a discharge current; and a charge/discharge switch,coupling the parasitic capacitors at the gate of the PMOS transistor tothe load terminal of the first current mirror or to the load terminal ofthe second current mirror.
 9. The phase change memory as claimed inclaim 8, wherein the charge/discharge circuit further comprises: a biascircuit; and a first digital-to-analog converter, biased by the biascircuit and receiving first digital data to generate the chargereference current.
 10. The phase change memory as claimed in claim 8,wherein the charge/discharge circuit further comprises: a bias circuit;and a second digital-to-analog converter, biased by the bias circuit andreceiving second digital data to generate the discharge referencecurrent.
 11. The phase change memory as claimed in claim 1, wherein thetransistor is an N-type metal oxide semiconductor (NMOS) transistor, andthe first, second and control terminals of the transistor are a drain, asource and a gate of the NMOS transistor, respectively.
 12. The phasechange memory as claimed in claim 11, wherein the control circuitcomprises: a capacitor, coupled to the control terminal of thetransistor; and a charge/discharge circuit, charging or discharging thecapacitor to vary the control signal between ground and a secondpre-determined voltage, wherein the second pre-determined voltage islower than a source voltage provided by the voltage source.
 13. Thephase change memory as claimed in claim 12, wherein the charge/dischargecircuit comprises: a first current mirror, having a power terminalbiased at the second pre-determined voltage, a reference currentterminal for a charge reference current to pass through, and a loadterminal outputting a charge current; a second current mirror, having apower terminal coupled to the ground, a reference terminal receiving adischarge reference current, and a load terminal providing a dischargecurrent; and a charge/discharge switch, coupling the capacitor to theload terminal of the first current minor or the load terminal of thesecond current minor.
 14. The phase change memory as claimed in claim13, wherein the charge/discharge circuit further comprises: a biascircuit; and a first digital-to-analog converter, biased by the biascircuit and receiving first digital data to generate the chargereference current.
 15. The phase change memory as claimed in claim 13,wherein the charge/discharge circuit further comprises: a bias circuit;and a second digital-to-analog converter, biased by the bias circuit andreceiving second digital data to generate the discharge referencecurrent.
 16. The phase change memory as claimed in claim 11, wherein thecontrol circuit comprises: a charge/discharge circuit, charging ordischarging parasitic capacitors at the gate of the NMOS transistor tovary the control signal between the ground and a second pre-determinedvoltage, wherein the second pre-determined voltage is lower than asource voltage provided by the voltage source.
 17. The phase changememory as claimed in claim 16, wherein the charge/discharge circuitcomprises: a first current mirror, having a power terminal biased at thesecond pre-determined voltage, a reference current terminal for a chargereference current to pass through, and a load terminal outputting acharge current; a second current minor, having a power terminal coupledto the grounded, a reference current terminal receiving a dischargereference current, and a load terminal providing a discharge current;and a charge/discharge switch, coupling the parasitic capacitors at thegate of the NMOS transistor to the load terminal of the first currentmirror or the load terminal of the second current minor.
 18. The phasechange memory as claimed in claim 17, wherein the charge/dischargecircuit further comprises: a bias circuit; and a first digital-to-analogconverter, biased by the bias circuit and receiving first digital datato generate the charge reference current.
 19. The phase change memory asclaimed in claim 17, wherein the charge/discharge circuit furthercomprises: a bias circuit; and a second digital-to-analog converter,biased by the bias circuit and receiving second digital data to generatethe discharge reference current.